The present invention relates to methods for forming wiring structures in electronic devices such as semiconductor devices.
Examples of known methods for forming wiring structures include a first prior art (see, for example, Japanese Laid-Open Publication No. 2000-277520) in which heat treatment (hereinafter, referred to as annealing) is performed before a chemical mechanical polishing (CMP) process and a second prior art (see, for example, Japanese Laid-Open Publication No. 11-186261) in which annealing is performed after a CMP process. Hereinafter, these two major known methods for forming wiring structures will be described with reference to the drawings with the case where wire is formed in a wiring groove formed in an insulating film taken an example.
FIGS. 9A through 9F are cross-sectional views showing respective process steps of a method for forming a wiring structure according to the first prior art in which “annealing” is performed “before a CMP process”.
First, as shown in FIG. 9A, a SiO2 insulating film 2 is deposited over a substrate 1, and then an etch stopper film 3 is formed. Subsequently, an interlayer dielectric film 4 of SiOF is formed. As will be described later, a groove for burying copper therein is provided in the interlayer dielectric film 4.
Next, as shown in FIG. 9B, a photoresist is applied onto the interlayer dielectric film 4, and then exposed to light and dissolved with a developer, leaving a resist mask 5 having an opening in its wiring groove region.
Thereafter, the interlayer dielectric film 4 is etched using the resist mask 5, thereby forming a groove 6 as shown in FIG. 9C. Then, the resist mask 5 is removed.
Subsequently, as shown in FIG. 9D, a barrier film 7 and a Cu sputtering film 8 are deposited in this order with a sputtering process over the substrate 1 having a groove pattern.
Then, as shown in FIG. 9E, a Cu plating film 9 is formed by, for example, an electrolytic plating process to fill the groove 6 completely. Subsequently, the Cu plating film 9 is annealed at a temperature of about 250 to 400° C. In this manner, the Cu sputter film 8 is merged with the Cu plating film 9.
Thereafter, as shown in FIG. 9F, respective parts of the Cu plating film 9 and the barrier film 7 located outside the groove 6 are removed with a CMP process, thereby exposing the surface of the interlayer dielectric film 4 as well as planalizing the respective surfaces of the interlayer dielectric film 4 and of the remaining part of the Cu plating film 9. In this manner, a copper wire made of copper buried in the groove 6 is formed.
FIGS. 10A through 10E are cross-sectional views showing respective process steps of a method for forming a wiring structure according to the second prior art in which “annealing” is performed “after a CMP process”.
First, as shown in FIG. 10A, an underlying oxide film 12 is deposited by a plasma CVD (chemical vapor deposition) process over a silicon substrate 11, and then a SiN film 13 and a SiO2 film 14 are deposited in this order with similar processes. Subsequently, the SiO2 film 14 is etched using a resist pattern (not shown) as a mask, thereby forming a recess reaching the SiN film 13. Thereafter, the resist pattern and exposed part of the SiN film 13 are removed, thereby forming a wiring groove 15.
Next, as shown in FIG. 10B, a barrier metal TaN film 16 is deposited by a sputtering process over the SiO2 film 14 provided with the wiring groove 15, and then a Cu seed film 17 is deposited over the barrier metal TaN film 16.
Thereafter, as shown in FIG. 10C, a Cu plating layer 18 is deposited by an electrolytic plating process over the SiO2 film 14 to fill the wiring groove 15 completely.
Subsequently, as shown in FIG. 10D, respective parts of the Cu plating layer 18, Cu seed film 17 and barrier metal TaN film 16 located outside the wiring groove 15 are removed by a CMP process, thereby exposing the surface of the SiO2 film 14. In this manner, a Cu buried wiring layer 19 is formed in the wiring groove 15.
Then, an annealing process is performed at a temperature of 300 to 500° C. for a holding time of 5 to 2000 seconds, thereby eliminating, for example, moisture, hydrogen and carbon dioxide contained in the Cu buried wiring layer 19 as well as increasing the grain size of the Cu buried wiring layer 19, as shown in FIG. 10E.
Through the foregoing process steps, a copper wire for a semiconductor device is formed.
However, the first and second prior arts have problems described later.
FIG. 11 is a view for explaining problems in the first prior art.
As shown in FIG. 11, a SiN film 23, a SiO2 film 24 and a FSG film (fluorine-doped silicon oxide film) 25 are formed in this order over an insulating film 21 in which a lower wiring layer 22 is buried. The SiN film 23, the SiO2 film 24 and the FSG film 25 are provided with a recess 26 and a wiring groove 27. More specifically, the recess 26 is made up of: a via hole 26a formed through the SiN film 23 and the SiO2 film 24 to reach the lower wiring layer 22; and a wiring groove 26b formed in the FSG film 25 and connected to the via hole 26a. The wiring groove 27 is also formed in the FSG film 25 in the same manner as the wiring groove 26b. A barrier film 28 is formed over the FSG film 25 to fill the recess 26 and the wiring groove 27 halfway. A copper film (a conducive film for upper wiring layer) 29 is further formed over the barrier film 28 to fill the recess 26 and the wiring groove 27 completely.
In the method for forming the wiring structure according to the first prior art, “annealing” is performed “before the CMP process”. Specifically, the copper film 29 is annealed before the CMP process for removing part of the copper film 29 that extends off the recess 26 and the wiring groove 27. However, in the first prior art, the annealing performed on the copper film 29 causes a problem that a void (cavity) 30 is created in the copper film to be a metal wiring layer as shown in FIG. 11.
The void 30 is considered to be created because of the following reasons. That is to say, in the first prior art in which “annealing” is performed “before the CMP process”, an annealing process is performed at a relatively high temperature of 250 to 400° C. before a CMP process in a state that the copper film 29 has a high volume. Accordingly, defects (e.g., vacancies at the atomic level existing along a grain boundary) contained in the copper film 29 just after the annealing gather in the via hole 26a, and in addition, the crystal growth of the copper film 29 is completed while these defects are not eliminated completely. This causes a void 30 in a narrow portion such as a via hole as shown in FIG. 11. As a result, the wiring resistance increases, thus reducing the yield of the semiconductor device and also degrading the reliability of the semiconductor device. Such a phenomenon is more remarkable when the width of a recess such as the wiring groove or via hole is 0.25 μm or less.
FIG. 12 is a view for explaining problems in the second prior art.
As shown in FIG. 12, a SiN film 43, a SiO2 film 44 and a FSG film 45 are formed in this order over an insulating film 41 in which a lower wiring layer 42 is buried. The SiN film 43, the SiO2 film 44 and the FSG film 45 are provided with a recess 46 and a wiring groove 47. More specifically, the recess 46 is made up of: a via hole 46a formed through the SiN film 43 and the SiO2 film 44 to reach the lower wiring layer 42; and a wiring groove 46b formed in the FSG film 45 and connected to the via hole 46a. The wiring groove 47 is also formed in the FSG film 45 as the wiring groove 46b. The recess 46 and the wiring groove 47 are filled with a copper film (a conducive film for upper wiring layer) 49 with a barrier film 48 interposed between the recess 46 or wiring groove 47 and the copper film 49. A SiN film 50 is formed on the FSG film 45 and the copper film 49.
According to the method for forming the wiring structure of the second prior art, “annealing” is performed “after the CMP process”. Specifically, the copper film 49 is annealed after the CMP process for removing part of the copper film 49 that extends off the recess 46 and the wiring groove 47. However, in the second prior art, the annealing performed on the copper film 49 causes a problem that a surface fracture 51 and a crack 52 are created in the surface of the copper film 49 buried in, for example, the recess 46, as shown in FIG. 12.
The surface fracture 51 and the crack 52 are considered to be created because of the following reasons. That is to say, in the second prior art in which “annealing” is performed “after the CMP process”, the copper film 49 buried in, for example, the recess 46 is annealed to have its crystal growth completed. Accordingly, defects contained in the copper film 49 gather in the surface of the copper film 49, which has been already planarized, and at the same time, the copper film 49 shrinks unevenly. This causes a surface fracture 51 and a crack 52 as shown in FIG. 12. Although the SiN film 50 is deposited over the entire surface of the wiring structure including the copper film 49 after the formation of the structure in the second prior art, the surface fracture 51 and the crack 52 are not filled with the SiN film 50 because the SiN film 50 has a low step coverage. Therefore, the surface defects such as the surface fracture 51 created in the surface of the copper film 49 to be a wire are left without being treated. As a result, these surface defects act as paths for surface diffusion of copper atoms, thus greatly deteriorating resistance to electromigration.